1. Field of the Invention
The present invention relates generally to an apparatus and a method for testing semiconductor devices such as integrated circuits. More particularly, the present invention is directed to a handler for placing an integrated circuit to be tested into an automatic circuit test apparatus while simultaneously protecting the circuit, being tested, from stray extraneous electromagnetic signals during the test thus preventing cross talk and other electromagnetic interference from inducing errors in the tested circuit.
2. Background of the Invention
The present invention generally relates to an automatic integrated circuit test apparatus provided with a means for protecting a circuit or device during test from being affected by extraneous electromagnetic signals such as alternating current (AC) interferences. This is achieved, in the present invention, by sealing all the avenues by which such signals can reach the circuit under test. This is especially achieved, in the present invention, by providing the tester with a unique handler that will, during the test, automatically encase the semiconductor circuit or device under test with a shield that attenuates or prevents extraneous electromagnetic signals that may cause test errors, from reaching the device being tested.
As is well known to the art, integrated circuits have a number of signal interface points or pins, herein after referred to as input/output pins, that are used to transfer data, in the form of electrical signals, into or out of the integrated circuits. During operation a select number of these pins are used to introduce the necessary control functions such as the circuit clocks, test modes, test control data, and etc. to the integrated circuit while the remaining signal interface pins are used to transfer data into and out of the data storage circuits contained in the integrated circuit.
At the present time, such AC defect testing requires the use of high frequency automated test equipment (ATE) that provides a tester contact for each signal interface pin on the integrated circuit, i.e., for both functional circuit pins and data storage pins. Often, under test conditions, the device being tested will function correctly in a direct current (DC) mode, that is, it will carry the proper current but, under AC test conditions, will exhibit false alternating current (AC) characteristics, e.g., the rise and fall times of signals will be altered such that the circuit appears to no longer meet its output specification. These false readings come about because extraneous electromagnetic signals from outside sources, such as adjacent testers, fluorescence lights, cell phones, nearby cell phone towers, radio security systems, and other modern electronic devices, can produce capacitively or inductively induce extraneous signals in the input/output pins of the device under test and thus create erroneous device outputs. These false readings result in either the scrapping of good devices or additional, more rigorous and/or extensive testing of the integrated circuit. In either case such false readings greatly increases the cost of such devices.
Furthermore as semiconductor chips or modules continue to increase in pin count and become faster they also become more sensitive to such extraneous electromagnetic signals. With every such an increase in sensitivity to stray electromagnetic signals testing of such devices has found to result in even more false test readings.
Even though the present high frequency, high pin count testers used in the industry are well designed, increasing sensitivity of the semiconductor devices or circuits to extraneous electromagnetic signals makes it increasingly difficult to provide automated test equipment that can speedily test the newer more complex integrated circuits without encountering the problems created by such extraneous electromagnetic signals.
With newer, higher storage capacity, and more sensitive integrated circuits the need of protecting them from such stray electromagnetic signals is even greater. None of the presently available automatic loading testers provide such protection.
Therefore, there are compelling economic reasons to provide a tester in which the integrated circuit being tested is protected from such extraneous electromagnetic signals during testing.